The present invention relates to semiconductor design, and more particularly, to a delay locked loop (DLL) circuit. Especially, the invention relates to a register controlled DLL that can perform a delay locking operation efficiently regardless of an operation frequency of a semiconductor device with a DLL circuit.
A synchronous semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) performs data transmission with external devices using an internal clock synchronized with an external clock input from an external device such as a memory controller.
This is because the time synchronization between an external clock applied to a memory from a memory controller and data output from the memory is greatly important to stably transmit the data between the memory and the memory controller.
Data from the memory are output in synchronization with an internal clock. The internal clock is applied in synchronization with the external clock when it is applied to the memory initially, however, it is somewhat delayed while passing through each element in the memory. Finally, the internal clock is asynchronous with the external clock when it is output to the outside of the memory.
Therefore, in order to stably transmit the data output from the memory, the internal clock that has been delayed while passing through each element in the memory should be synchronized with the external clock at an edge or a center of the external clock by adjusting a data loading time on a bus to the internal clock for accurately positioning the internal clock.
A clock synchronization circuit of synchronizing the internal clock with the external clock is a phase locked loop (PLL) or a delay locked loop (DLL).
Specifically, when the external clock differs in frequency from the internal clock signal, it is necessary to employ a frequency multiplication function. Thus, the PLL is mainly used in this case. However, when the external clock signal is equal in frequency to the internal clock signal, the DLL is mainly used because the DLL is not greatly affected by a noise and also can be implemented in a relatively small area in comparison with the PLL.
Since a semiconductor memory device uses the same frequency for the external and internal clocks, the DLL is mainly used as a clock synchronization circuit.
Among various kinds of the DLLs, the most recent technology provides a register controlled DLL circuit capable of reducing a time that is taken in locking a first clock. In detail, the register controlled DLL circuit having a register capable of storing a locked delay value, stores the locked delay value in the register when a power is interrupted, and loads the locked delay value stored in the register when the power is turned on again so that the locked delay value is instantly used for locking the clock.
FIG. 1 is a block diagram of a conventional register controlled DLL circuit.
Referring to FIG. 1, the conventional register controlled DLL circuit includes a clock buffer 100, a divider 180, a phase comparator 120, a clock delay circuit 140, and a delay replica model 160. The clock buffer 100 buffers a source clock signal CLK and a source clock bar signal CLKB, which are output from the outside. The divider 180 divides a frequency of a reference clock REFCLK synchronized with a clock edge of the source clock signal CLK at a predetermined ratio to output a divided reference clock REFCLK_DIV. The phase comparator 120 compares phases of the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK with each other. The clock delay circuit 140 delays a phase of a first internal clock RCLK synchronized with a clock edge of the source clock signal CLK, a phase of a second internal clock FCLK synchronized with a clock edge of the source clock bar signal CLKB, and a phase of the divided reference clock REFCLK_DIV by delay durations according to a comparison signal PHASE_COMP of the phase comparator 120. The delay replica model 160 reflects actual delay conditions of the source clock signals CLK and CLKB in a delayed divided reference clock REFCLK_DIV_DELAY of the clock delay circuit 140 corresponding to the input divided reference clock REFCLK_DIV.
The clock buffer 100 includes a first clock buffer 102 configured to buffer the source clock signal CLK to output the first internal clock RCLK, a second clock buffer 104 configured to buffer the source clock bar signal CLKB to output the second internal clock FCLK, and a dummy clock buffer 106 configured to buffer the source clock signal CLK to output the reference clock REFCLK.
The clock delay circuit 140 includes a rising clock delay 142, a falling clock delay 144, a dummy delay 146, and a delay controller 148. The rising clock delay 142 delays the phase of the first internal clock RCLK in response to a delay control signal DELAY_CON, and a falling clock delay 144 delays the phase of the second internal clock FCLK in response to the delay control signal DELAY_CON. The dummy delay 146 delays the phase of the divided reference clock REFCLK_DIV_DELAY in response to the delay control signal DELAY_CON. The delay controller 148 changes a logic level of the delay control signal DELAY_CON in response to the comparison signal PHASE_COMP of the phase comparator 120.
Herebelow are operations of the conventional register controlled DLL circuit having the above configuration.
From the clock buffer 100 configured to buffer the source clock signal CLK and the source clock bar signal CLKB, the first internal clock RCLK and the reference clock REFCLK are output in synchronization with the source clock signal CLK, and the second internal clock FCLK is output in synchronization with the source clock bar signal CLKB. Since the source clock signal CLK is opposite in phase to the source clock bar signal CLKB, the first internal clock RCLK and the reference clock REFCLK are opposite in phase to the second internal clock FCLK.
Therefore, on the basis of the source clock signal CLK, the first internal clock RCLK and the reference clock REFCLK are synchronized with a rising edge of the source clock signal CLK, and the second source clock FCLK is synchronized with a falling edge of the source clock signal CLK.
In the conventional register controlled DLL circuit, the divider 180 configured to divide the frequency of the reference clock REFCLK at a predetermined ratio is employed to reduce power consumption.
That is, the reference clock REFCLK is used to control the operation of the conventional register controlled DLL circuit through phase comparison with the feedback clock FEEDBACK_CLK. If the source clock signal CLK and the source clock bar signal CLKB input from the outside have high frequencies, the reference clock REFCLK and the feedback clock FEEDBACK_CLK also have high frequencies. When comparing phases of the reference clock REFCLK and the feedback clock FEEDBACK_CLK with each other, power consumption becomes larger as the frequencies of the reference clock REFCLK and the feedback clock FEEDBACK_CLK are higher. Accordingly, the conventional register controlled DLL circuit employs a power-saving method of reducing power consumption by performing a phase comparison using the divided reference clock REFCLK_DIV if the external source clock signals CLK and CLKB have high frequencies.
For the aforesaid reason, the conventional register controlled DLL circuit employs the divider 180 between the dummy clock buffer 106 and the phase comparator 120, and thus the phase comparison is performed using the divided reference clock REFCLK_DIV that is obtained by dividing the reference clock REFCLK at a predetermined ratio, instead of directly using the reference clock REFCLK synchronized with the clock edge of the source clock signal CLK. The predetermined ratio is 1/N (N is a natural number greater than 2), generally 4 or 8.
The phase comparator 120, which compares phases of the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK with each other, changes a value of the comparison signal PHASE_COMP depending on a phase difference between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK, thereby controlling the operation of the conventional register controlled DLL circuit.
For example, if the phase difference between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK deviates from a predetermined range so that the phase difference becomes relatively great, a first signal value of the comparison signal PHASE_COMP is changed, thus allowing a fast mode operation to be performed.
On the contrary, if the phase difference between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK deviates from the predetermined range so that the phase difference becomes relatively small, a second signal value of the comparison signal PHASE_COMP is changed, allowing a normal mode operation to be performed.
If the phase difference between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK does not deviate from the predetermined range, a third signal value of the comparison signal PHASE_COMP is changed, allowing a fine mode operation to be performed.
The clock delay circuit 140 performs the following operations in response to the operation of the phase comparator 120. In the fast mode operation, the clock delay circuit 140 delays the phases of the first internal clock RCLK, the second internal clock FCLK and the divided reference clock REFCLK_DIV by a predetermined delay duration of a delay unit group having a plurality of delay units according to the variation of the first signal value of the comparison signal PHASE_COMP.
In the normal mode operation, the clock delay circuit 140 delays the phases of the first internal clock RCLK, the second internal clock FCLK and the divided reference clock REFCLK_DIV using delay units according to the variation of the second signal value of the comparison signal PHASE_COMP.
In the fine mode operation, the clock delay circuit 140 delays the phases of the first internal clock RCLK, the second internal clock FCLK and the divided reference clock REFCLK_DIV by divided delay durations according as the second signal value of the comparison signal PHASE_COMP varies. Herein, the divided delay durations are obtained by dividing a delay duration of a delay unit into the predetermined number.
FIG. 2 is a block diagram illustrating the delay units 142, 144 and 146 of the clock delay circuit 140 in the conventional register controlled DLL circuit of FIG. 1.
Referring to FIG. 2, each of the delay units 142, 144 and 146 of the clock delay circuit 140 in the conventional register controlled DLL circuit includes a first delay line 200, a second delay line 220, and a phase mixer 240. The first delay line 200 includes a plurality of delay units DU1, DU2, DU3, DU4, DU5, DU6, DU7 and DU8 connected in series, and delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV through the odd-numbered delay units that are selected in predetermined sequence in response to the delay control signal DELAY_CON. The second delay line 220 includes a plurality of delay units DU1, DU2, DU3, DU4, DU5, DU6, DU7 and DU8 connected in series, and delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV through the even-numbered delay units that are selected in predetermined sequence in response to the delay control signal DELAY_CON. The phase mixer 240 mixes a phase of a clock DU_CLK_1 output from the first delay 200 and a phase of the clock DU_CLK_2 output from the second delay line 220 at a mixing ratio varying according to the delay control signal DELAY_CON.
The phase mixer 240 includes a first inversion-driving unit 242, a second inversion-driving unit 244, and a third inversion-driving unit 246. The first inversion-driving unit 242 inverts and drives the output clock DU_CLK_1 of the first delay line 200 to apply the inverted clock to an output node OUT_NODE with an ability to drive that varies according to the delay control signal DELAY_CON. The second inversion-driving unit 244 inverts and drives the output clock DU_CLK_2 of the second delay line 220 to apply the inverted clock to the output node OUT_NODE with an ability to drive that varies according to the delay control signal DELAY_CON. The third inversion-driving unit 246 inverts and drives a clock of the output node OUT_NODE with a predetermined ability to drive.
Herebelow are operations of the delay units 142, 144 and 146 of the clock delay unit 140 in the conventional register controlled DLL circuit.
First, the first delay line 200 selects the odd-numbered delay units DU1, DU3, DU5 and DU7 among the plurality of delay units DU1, DU2, DU3, DU4, DU5, DU6, DU7 and DU8 in response to the delay control signal DELAY_CON in predetermined sequence. That is, the first delay line 200 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by the point “1”, “3”, “5” or “7”.
The predetermined sequence may differ according to an operation mode of the clock delay circuit 140. In the fast mode, the first delay unit DU1 corresponding to the point “1” among the odd-numbered delay units DU1, DU3, DU5 and DU7 of the first delay line 200 is selected first, and then the fifth delay unit DU5 corresponding to the point “5” is selected. That is, the first delay line 200 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by a delay duration of <½×delay unit> corresponding to the point “1” or by a delay duration of <(4+½)×delay unit> corresponding to the point “5”.
In the normal mode, the first delay unit DU1 corresponding to the point “1” among the odd-numbered delay units DU1, DU3, DU5 and DU7 of the first delay line 200 is selected first; then the third delay unit DU3 corresponding to the point “3” is selected; thereafter the fifth delay unit DU5 corresponding to the point “5” is selected; and finally the seventh delay unit DU7 corresponding to the point “7” is selected. That is, the first delay line 200 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by a delay duration of <½×delay unit> corresponding to the point “1”, by a delay duration of <(2+½)×delay unit> corresponding to the point “3”, by a delay duration of <(4+½)×delay unit> corresponding to the point “5”, or by a delay duration of <(6+½)×delay unit> corresponding to the point “7”.
In the fine mode, the delay units selected during the normal mode among the odd-numbered delay units DU1, DU3, DU5 and DU7 of the first delay line 200 are maintained as they are. In this mode, the first delay line 200 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV to by a delay duration smaller than the delay duration of the delay unit, which will be more fully described together with description for operation of the phase mixer 240 later.
The second delay line 220 selects the even-numbered delay units DU2, DU4, DU6 and DU8 among the plurality of delay units DU1, DU2, DU3, DU4, DU5, DU6, DU7 and DU8 in response to the delay control signal DELAY_CON in predetermined sequence. That is, the second delay line 220 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by the point “2”, “4”, “6” or “8”.
The predetermined sequence may differ according to an operation mode of the clock delay circuit 140. In the fast mode, the second delay unit DU2 corresponding to the point “2” among the even-numbered delay units DU2, DU4, DU6 and DU8 of the second delay line 220 is selected first, and then the sixth delay unit DU6 corresponding to the point “6” is selected. That is, the second delay line 220 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by a delay duration of <(1+½)×delay unit> corresponding to the point “2” or by a delay duration of <(5+½)×delay unit> corresponding to the point “6”.
In the normal mode, the second delay unit DU2 corresponding to the point “2” among the even-numbered delay units DU2, DU4, DU6 and DU8 of the second delay line 220 is selected first; then the fourth delay unit DU4 corresponding to the point “4” is selected; thereafter the sixth delay unit DU6 corresponding to the point “6” is selected; and finally the eighth delay unit DU8 corresponding to the point “8” is selected. That is, the second delay line 220 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by a delay duration of <(1+½)×delay unit> corresponding to the point “2”, by a delay duration of <(3+½)×delay unit> corresponding to the point “4”, by a delay duration of <(5+½)×delay unit> corresponding to the point “6”, or by a delay duration of <(7+½)×delay unit> corresponding to the point “8”.
In the fine mode, the delay units selected during the normal mode among the even-numbered delay units DU2, DU4, DU6 and DU8 of the second delay line 220 are maintained as they are. The second delay line 220 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV a delay duration smaller than the delay duration of the delay unit, which will also be more fully described together with description for operation of the phase mixer 240 later.
The phase mixer 240 mixes the output clock DU_CLK_1 of the first delay line 200 and the output clock DU_CLK_2 of the second delay line 220 at a mixing ratio corresponding to the delay control signal DELAY_CON.
The mixing ratio corresponding to the delay control signal DELAY_COM varies according to operation of the clock delay unit 140. In the fast mode and the normal mode, the phase mixer 240 mixes the phase of the output clock DU_CLK_1 of the first delay line 200 and the phase of the output clock DU_CLK_2 of the second delay line 220 at a mixing ratio of 1:1.
For example, when the phase of the output clock DU_CLK_1 of the first delay line 200 is delayed by a delay duration of <½×delay unit> corresponding to the point “1”, and the phase of the output clock DU_CLK_2 of the second delay line 220 is delayed by a delay duration of <(1+½)×delay unit> corresponding to the point “2”, the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV is delayed by a delay duration of <1×delay unit> corresponding to the center between the points “1” and “2” so that a delayed first internal clock RCLK_DELAY, a delayed second internal clock FCLK_DELAY or a delayed divided reference clock REFCLK_DIV_DELAY, which has the delay duration of <1×delay unit>, is output from the phase mixer 240.
Likewise, when the phase of the output clock DU_CLK_1 of the first delay line 200 is delayed by a delay duration of <(4+½)×delay unit> corresponding to the point “5”, and the phase of the output clock DU_CLK_2 of the second delay line 220 is delayed by a delay duration of <(5+½)×delay unit> corresponding to the point “6”, the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV is delayed by a delay duration of <5×delay unit> corresponding to the center between the points “5” and “6” so that a delayed first internal clock RCLK_DELAY, a delayed second internal clock FCLK_DELAY or a delayed divided reference clock REFCLK_DIV_DELAY, which has the delay duration of <5×delay unit>, is output from the phase mixer 240.
In the fine mode, the phase of the output clock DU_CLK_1 of the first delay line 200 and the phase of the output clock DU_CLK_2 of the second delay line 220 are mixed at a mixing ratio varying according to the delay control signal.
For example, even in the case where the phase of the output clock DU_CLK_1 of the first delay line 200 is delayed by a delay duration of <½×delay unit> corresponding to the point “1”, and the phase of the output clock DU_CLK_2 of the second delay line 220 is delayed by a delay duration of <(1+½)×delay unit> corresponding to the point “2”, the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV can be delayed by a delay duration of <¾×delay unit> corresponding to ¼ point between the points “1” and “2” so that a delayed first internal clock RCLK_DELAY, a delayed second internal clock FCLK_DELAY or a delayed divided reference clock REFCLK_DIV_DELAY, which has the delay duration of <¾×delay unit>, is output from the phase mixer 240, if the mixing ratio is set such that the output clock DU_CLK_1 of the first delay line 200 is 75% and the output clock DU_CLK_2 of the second delay line 220 is 25%.
In this case, if the mixing ratio is set such that the output clock DU_CLK_1 of the first delay line 200 is 25% and the output clock DU_CLK_2 of the second delay line 220 is 75%, the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV can be delayed by a delay duration of <(1+¼)×delay unit> corresponding to ¾ point between the points “1” and “2” so that a delayed first internal clock RCLK_DELAY, a delayed second internal clock FCLK_DELAY or a delayed divided reference clock REFCLK_DIV_DELAY, which has the delay duration of <(1+¼)×delay unit>, is output from the phase mixer 240.
As described above, the conventional register controlled DLL circuit appropriately controls the delay control signal DELAY_CON according to an operation mode, making it possible to select a delay duration smaller than the delay duration of the delay unit.
FIG. 3 illustrates a problem arising in operation of the delay unit of the clock delay circuit 140 in the conventional register controlled DLL circuit of FIG. 1.
Referring to FIG. 3, the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK, which have different frequencies from each other, are input to the delay units 142, 144 and 146 of the clock delay circuit 140 in the conventional register controlled DLL circuit of FIG. 1.
When the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK have low frequencies (see LOW FREG_LOCK in FIG. 3A), it can be appreciated that the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK have relatively long periods. Hence, a delay duration between the feedback clock FEEDBACK_CLK and the divided reference clock REFCLK_DIV for performing a delay locking operation is relatively large.
Therefore, the delay units 142, 144 and 146 of the clock delay circuit 140 delay the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by a relatively large delay duration, and then output the delayed first internal clock RCLK_DELAY, the delayed second internal clock FCLK_DELAY or the delayed divided reference clock REFCLK_DIV_DELAY.
Specifically, in the first delay line 200 of each of the delay units 142, 144 and 146 in the clock delay circuit 140, the delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK is smaller than the delay duration corresponding to the point “7” and greater than the delay duration corresponding to the point “5”, but closer to the delay duration corresponding to the point “7”. Consequently, the point “5” is selected in the fast mode, and the point “7” is selected in the normal mode.
In the second delay line 220 of each of the delay units 142, 144 and 146 in the clock delay circuit 140, the delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK is smaller than the delay duration corresponding to the point “8” and greater than the delay duration corresponding to the point “6”, but closer to the delay duration corresponding to the point “6”. Consequently, the point “6” is selected in the fast mode, and the point “6” is also selected in the normal mode.
In the fine mode, the phase mixer 240 of each of the delay units 142, 144 and 146 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV in units of a divided delay duration, e.g., a delay duration of <¼×delay unit> in FIG. 3, according to the delay control signal DELAY_CON. Herein, the divided delay duration is obtained by dividing a difference between the delay duration corresponding to the point “7” selected by the first delay line 200 in the normal mode and the delay duration corresponding to the point “6” selected by the second delay line 220 in the normal mode into a predetermined number, e.g., 4.
A delay duration between the feedback clock FEEDBACK_CLK and the divided reference clock REFCLK_DIV, allowing the delay locking operation to be performed in the fine mode operation of the phase mixer 240, may vary in units of a delay duration of <¼×delay unit> between the delay duration of <(6+½)×delay unit> corresponding to the point “7” and the delay duration of <(5+½)×delay unit> corresponding to the point “6”. That is, compared to the maximum delay duration and the minimum delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK, the variable delay duration due to the fine mode operation of the phase mixer 240 is relatively small.
Therefore, when the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK have relatively low frequencies, it is possible to finely adjust the delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK to perform the delay locking operation through the fine mode operation of the phase mixer 240.
In contrast, when the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK have high frequencies (see HIGH FREG_LOCK in FIG. 3B), it can be appreciated that the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK have relatively short periods. Hence, a delay duration between the feedback clock FEEDBACK_CLK and the divided reference clock REFCLK_DIV for performing a delay locking operation is relatively small.
Therefore, the delay units 142, 144 and 146 of the clock delay circuit 140 delay the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV by a relatively small delay duration, and then output the delayed first internal clock RCLK_DELAY, the delayed second internal clock FCLK_DELAY or the delayed divided reference clock REFCLK_DIV_DELAY.
Specifically, in the first delay line 200 of each of the delay units 142, 144 and 146 in the clock delay circuit 140, the delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK is smaller than the delay duration corresponding to the point “3” and greater than the delay duration corresponding to the point “1”, but closer to the delay duration corresponding to the point “3”. Consequently, the point “1” is selected in the fast mode, and the point “3” is selected in the normal mode.
In the second delay line 220 of each of the delay units 142, 144 and 146 in the clock delay circuit 140, the delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK is smaller than the delay duration corresponding to the point “4” and greater than the delay duration corresponding to the point “2”, but closer to the delay duration corresponding to the point “2”. Consequently, the point “2” is selected in the fast mode, and the point “2” is also selected in the normal mode.
In the fine mode, the phase mixer 240 of each of the delay units 142, 144 and 146 delays the first internal clock RCLK, the second internal clock FCLK or the divided reference clock REFCLK_DIV in units of a divided delay duration, e.g., a delay duration of <¼×delay unit> in FIG. 3, according to the delay control signal DELAY_CON. Herein, the divided delay duration is obtained by dividing a difference between the delay duration corresponding to the point “3” selected by the first delay line 200 in the normal mode and the delay duration corresponding to the point “2” selected by the second delay line 220 in the normal mode into a predetermined number, e.g., 4.
A delay duration between the feedback clock FEEDBACK_CLK and the divided reference clock REFCLK_DIV, allowing the delay locking operation to be performed in the fine mode operation of the phase mixer 240, may vary in units of a delay duration of <¼×delay unit> between the delay duration of <(2+½)×delay unit> corresponding to the point “3” and the delay duration of <(1+½)×delay unit> corresponding to the point “2”. That is, compared to the maximum delay duration and the minimum delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK, the variable delay duration due to the fine mode operation of the phase mixer 240 is relatively large.
Therefore, when the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK have relatively high frequencies, it is difficult to finely adjust the delay duration between the divided reference clock REFCLK_DIV and the feedback clock FEEDBACK_CLK to perform the delay locking operation through the fine mode operation of the phase mixer 240.
Consequently, in an environment where high-frequency source clock signals CLK and CLKB are used, a jitter with a relatively high value is generated between the delayed first internal clock RCLK_DELAY and the second internal clock FCLK_DELAY although the conventional register controlled DLL circuit has performed a delay locking operation.